library verilog;
use verilog.vl_types.all;
entity cnt100_vlg_sample_tst is
    port(
        CLK_021         : in     vl_logic;
        sw_clear_021    : in     vl_logic;
        sw_stop_021     : in     vl_logic;
        sampler_tx      : out    vl_logic
    );
end cnt100_vlg_sample_tst;
